1. Field of the Invention
The present invention generally relates to a memory device, and more particularly, to a flash memory device in which program and erase operations can be performed at the same time by dividing a bank.
2. Discussion of Related Art
A NAND flash memory in the related art can implement a very small cell area and is therefore suitable for high-integrated memory devices. However, the NAND flash memory is disadvantageous in that a time taken to read first data is long and a programming time is also long. Furthermore, it cannot perform other operations while performing one operation.
FIG. 1 is a block diagram illustrating the bank structure of a NAND flash memory in the related art.
Referring to FIG. 1, in the NAND flash memory, a X-decoder 20 provided between cell arrays 10 on one P-well is driven through word lines within the cell array 10. Data is transferred to page buffers 30 through cache buffers 40. While selected pages are programmed, data for performing a next page program are transferred to the cache buffers 40. Accordingly, the related art single bank structure can improve the read and program speeds.
If the cache buffers 40 are used, a data input operation can be performed while a program operation is performed. Furthermore, while data are output, a next page can be read by the page buffer 30.
In this case, however, there still remains a problem in that other operations cannot be performed while the read, program or erase operation is performed.